1. Field of the Invention
The present invention generally relates to a signal receiver circuit, in particular, to a signal receiver circuit which can output a full-swing output signal.
2. Description of Related Art
Regarding a signal receiver circuit in a dynamic random access memory (DRAM), if N-type metal oxide semiconductor (NMOS) transistors in N-type differential amplifiers have high threshold voltage, current restriction issues may limit the operation of the entire circuit, and the duty cycle of the signal receiver circuit may be unbalanced.
FIG. 1 illustrates a conventional signal receiver circuit. The signal receiver circuit includes transistors M1˜M4, an inverter INVR, and a resistor RD. The gate of the transistor M1 is coupled to a node N1, the source thereof is coupled to a voltage source VDD, and the drain thereof is coupled to both the input terminal of the inverter INVR and the drain of the transistor M3. The gate of the transistor M2 is coupled to the node N1, the source thereof is coupled to the voltage source VDD, and the drain thereof is coupled to the node N1.
The gate of the transistor M3 is coupled to an input voltage VIN, the source thereof is coupled to both the first terminal of the resistor RD and the source of the transistor M4, and the drain thereof is coupled to both the input terminal of the inverter INVR and the drain of the transistor M1. The gate of the transistor M4 is coupled to a reference voltage VREF, the source thereof is coupled to both the first terminal of the resistor RD and the source of the transistor M3, and the drain thereof is coupled to the node N1. The first terminal of the resistor RD is coupled to both the sources of the transistors M3 and M4, and the second terminal thereof is coupled to ground. The input terminal of the inverter INVR is coupled to both the drains of the transistors M1 and M3, and the output terminal thereof outputs an output voltage Vout.
The reference voltage VREF is half of the voltage source VDD. If the voltage source VDD is 1.5V, then the reference voltage VREF is 0.75V. When the input voltage VIN is 0.925V, the output terminal Vout outputs a signal of 1.5V (i.e. logic high level). If the input voltage VIN is 0.575V, the output terminal Vout outputs a signal of 0V (i.e. logic low level). Because the threshold voltage of the transistor M3 is high and the voltage VGS between the gate and the source thereof is restricted by the input voltage VIN, the drain-source current IDS of the transistor M3 is not sufficient for supporting full swing at the input terminal of the inverter INVR, which causes unbalanced duty cycle of the output voltage Vout (i.e., the duty cycle of the output voltage Vout cannot reach 50%).
As described above, a signal receiver circuit, which can boost the input voltage VIN, namely, increases the gate-source voltage VGS of the transistor M3, and accordingly can provide a high drain-source current IDS and balance the duty cycle of the output voltage, is to be provided.